DocumentCode :
114849
Title :
An ultra-low power and area efficient 10 bit digital to analog converter architecture
Author :
Binti Sharuddin, Iffa ; Lee, Lun-Hui
Author_Institution :
Fac. of Eng., Multimedia Univ., Cyberjaya, Malaysia
fYear :
2014
fDate :
27-29 Aug. 2014
Firstpage :
305
Lastpage :
308
Abstract :
An ultra-low power and area efficient successive approximation register (SAR) analog-to-digital converter (ADC) is presented. To achieve ultra-low power performance, a digital-to-analog converter (DAC) architecture is proposed that combined a 4-bit thermometer coded and a 6-bit C-2C array to form a 10-bit DAC. Thereby, power consumption and area of the design are drastically reduced by virtue of lower switching activity and smaller size capacitor array. Add on to that, the architecture also has better linearity. The proposed 10-bit DAC is designed and simulated in a 0.18 μm CMOS process. Simulation results show that it only consumed 1.74 nW at 1.5 V power supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; digital-analogue conversion; low-power electronics; thermometers; ADC; C-2C array; CMOS process; DAC architecture; SAR; analog-to-digital converter; area efficient successive approximation register; digital to analog converter architecture; power 1.74 nW; size 0.18 mum; thermometer; ultra-low power performance; voltage 1.5 V; word length 10 bit; word length 4 bit; word length 6 bit; Arrays; Capacitance; Capacitors; Linearity; Low-power electronics; Power demand; Switches; analog-to-digital converter; successive approximation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Electronics (ICSE), 2014 IEEE International Conference on
Conference_Location :
Kuala Lumpur
Type :
conf
DOI :
10.1109/SMELEC.2014.6920858
Filename :
6920858
Link To Document :
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