Title :
A Fully Parallel Mixed-Radix Conversion Algorithm for Residue Number Applications
Author_Institution :
Communication Sciences Laboratory, Lockheed Palo Alto Research Laboratory
fDate :
4/1/1983 12:00:00 AM
Abstract :
A new, fully parallel mixed-radix conversion (MRC) algorithm which utilizes the maximum parallelism that exists in the residues (RNS) to mixed-radix (MR) digits conversion to achieve high throughput rate and very short conversion time is presented. The new algorithm has a conversion time of two table look-up cycles for moduli sets consisting of up to 15 moduli. As a comparison, the classical Szabo and Tanaka MRC algorithm has a conversion time of (n − 1) clock cycles for an n-moduli RNS. This algorithm can be implemented by off-the-shelf ECL IC´s to achieve a conversion time of 50 ns and a throughput rate of 40 MHz for a 150-bit RNS.
Keywords :
General computing; mixed-radix conversion; parallel and pipelined architecture; residue number system; Clocks; Computer architecture; Concurrent computing; Delay; Digital arithmetic; Hardware; Parallel processing; Signal processing algorithms; Throughput; Very large scale integration; General computing; mixed-radix conversion; parallel and pipelined architecture; residue number system;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1983.1676242
