Title :
A low power 0.18μm CMOS technology integrating dual-slope analog-to digital converter
Author :
Halim, Ili Shairah Abd ; Yusof, Nor Syazwana Mohd ; Hassan, Siti Lailatul Mohd
Author_Institution :
Fac. of Electr. Eng., Univ. Teknol. MARA, Shah Alam, Malaysia
Abstract :
In this paper, a 4-bit integrating dual slope analog-to digital converter (DS-ADC) is designed which consumes low power and simplicity but slow conversion time. The design utilizing a Silvaco Electronic Design Automation (SEDA) tools with an advanced 0.18μm CMOS Technology using 1.8V power supply. This integrating dual slope ADC contains five main components, which are switching, integrator, comparator, control logic and counter at which the integrator is realized with a two-stage operational amplifier (op-amp) that provides sufficient gain, ICMR and low power dissipation. Simulation confirms that the proposed DS-ADC architecture shows a power efficiency of 2.4739mW with 1.06μs conversion time.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; electronic design automation; low-power electronics; DS-ADC architecture; ICMR; SEDA tools; Silvaco electronic design automation tool; comparator; control logic; counter; dual-slope analog-to digital converter; integrator; low power CMOS technology; low power dissipation; op-amp; power 2.4739 mW; power supply; size 0.18 mum; switching; time 1.06 mus; two-stage operational amplifier; voltage 1.8 V; word length 4 bit; CMOS integrated circuits; Capacitors; Clocks; Educational institutions; Logic gates; Radiation detectors; Switches; Comparator; Control Logic; Dual Slope ADC; Integrator; Two stage op-amp;
Conference_Titel :
Semiconductor Electronics (ICSE), 2014 IEEE International Conference on
Conference_Location :
Kuala Lumpur
DOI :
10.1109/SMELEC.2014.6920861
