• DocumentCode
    1148648
  • Title

    Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains

  • Author

    Rao, K. V S S Prasad ; Basu, Dhruba

  • Author_Institution
    Digital Processors Laboratory, Electronics Systems Division, Vikram Sarabhai Space Centre
  • Issue
    5
  • fYear
    1983
  • fDate
    5/1/1983 12:00:00 AM
  • Firstpage
    464
  • Lastpage
    475
  • Abstract
    All the totally self checking (TSC) circuits known so far [3]-[8] restrict their fault sets to either single or multiple but unidirectional stuck-at faults. Meyer and Sundstrom [20] have considered on line diagnosis of unrestricted faults but the class of circuits proposed by them does not fall under the category of TSC circuits. This paper proposes a new type of circuit model which is TSC for a fault set, consisting of all possible, i.e., unrestricted stuck-at faults on all the gate input and output signal lines. The model uses redundancy in both space and time domains and realizes combinatorial functions. Some important properties of the model are brought out by a set of lemmas and theorems. The viability of the model is demonstrated by a circuit example which uses CMOS technology.
  • Keywords
    CMOS; combinatorial logic; multiple faults; self-checking circuits; self-dual function; space domain redundancy; time domain redundancy; Built-in self-test; CMOS logic circuits; CMOS technology; Circuit faults; DH-HEMTs; Fault diagnosis; Logic circuits; Redundancy; Semiconductor device modeling; Space technology; CMOS; combinatorial logic; multiple faults; self-checking circuits; self-dual function; space domain redundancy; time domain redundancy;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1983.1676257
  • Filename
    1676257