DocumentCode :
1148728
Title :
Electrical/Mechanical Modeling, Reliability Assessment, and Fabrication of FlexConnects: A MEMS-Based Compliant Chip-to-Substrate Interconnect
Author :
Kacker, Karan ; Sitaraman, Suresh K.
Author_Institution :
Comput.-Aided Simulation of Packaging Reliability Lab., Georgia Inst. of Technol., Atlanta, GA
Volume :
18
Issue :
2
fYear :
2009
fDate :
4/1/2009 12:00:00 AM
Firstpage :
322
Lastpage :
331
Abstract :
Compliant free-standing structures can be used as chip-to-substrate interconnects. Such ldquocompliant interconnectsrdquo are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. In our previous work, we have proposed a new compliant interconnect technology called FlexConnect to address these concerns with compliant interconnects. An innovative cost-effective MEMS-based fabrication process is used to fabricate these compliant interconnects. Sequential lithography and electroplating processes with up to two masking steps are utilized. Utilizing the proposed fabrication process, in this paper, FlexConnects are realized at a 100-mum pitch. High-frequency modeling of the electrical parasitics of the interconnect is performed. Through finite-element-based models, the advantage of using multiple electrical paths as part of the interconnect design is shown from a thermomechanical reliability perspective. Finally, taking advantage of the MEMS-based photolithographic fabrication process, a heterogeneous combination of FlexConnects and column interconnects is proposed. This approach is shown to be an additional avenue to attain improved electrical performance without compromising mechanical performance.
Keywords :
electroplating; integrated circuit interconnections; integrated circuit reliability; micromechanical devices; photolithography; wafer level packaging; FlexConnects; MEMS-based chip-to-substrate interconnect; compliant interconnects; electroplating processes; photolithography; reliability assessment; sequential lithography; size 100 mum; wafer level packaging; Chip-to-substrate interconnects; compliant interconnects; first-level interconnects; wafer-level packaging (WLP);
fLanguage :
English
Journal_Title :
Microelectromechanical Systems, Journal of
Publisher :
ieee
ISSN :
1057-7157
Type :
jour
DOI :
10.1109/JMEMS.2008.2011117
Filename :
4776493
Link To Document :
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