DocumentCode
1148762
Title
Oct-tree-based multilevel low-rank decomposition algorithm for rapid 3-D parasitic extraction
Author
Gope, Dipanjan ; Jandhyala, Vikram
Author_Institution
Electr. Eng. Dept., Univ. of Washington, Seattle, WA, USA
Volume
23
Issue
11
fYear
2004
Firstpage
1575
Lastpage
1580
Abstract
Fast parasitic extraction is an integral part of high-speed microelectronic simulation at the package and on-chip level. Integral equation methods and related fast solvers for the iterative solution of the resulting dense matrix systems have enabled linear time complexity and memory usage. However, these methods tend to have large disparities between setup and matrix-vector product times that affect their efficiency when applied to multiple excitation problems, i.e., problems with a large number of nets. For example, FastCap, which is based on the fast multipole method, has a significantly faster setup time than the multilevel QR decomposition-based IES3, but relatively slow matrix-vector products. In this paper, we present a novel oct-tree-based QR compression technique for fast iterative solution. The regular cube structure of the fast multipole method and the QR compression scheme for interaction submatrices as in IES3 are combined to achieve a predetermined compressible matrix-block structure and, consequently, superior memory, setup, and solve time efficiencies.
Keywords
circuit complexity; circuit simulation; high-speed techniques; integral equations; iterative methods; matrix decomposition; octrees; FastCap; QR compression technique; cube structure; dense matrix systems; fast multipole method; high-speed microelectronic simulation; integral equation methods; interaction submatrices; iterative solution; linear time complexity; memory usage; multilevel QR decomposition-based IES3; oct-tree-based multilevel low-rank decomposition algorithm; rapid 3D parasitic extraction; Delay estimation; Frequency estimation; Integral equations; Iterative algorithms; Iterative methods; Matrix decomposition; Microelectronics; Packaging; Parasitic capacitance; Wire; 65; Low-rank-decomposition; oct-tree multilevel hierarchy; parasitic extraction;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2004.836723
Filename
1350883
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