Title :
A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays
Author :
Ramanatha, K.S. ; Biswas, Nripendra N.
Author_Institution :
Department of Electrical Engineering, Government B.. . College of Engineering
fDate :
6/1/1983 12:00:00 AM
Abstract :
In this paper, the validity of single fault assumption in deriving diagnostic test sets is examined with respect to crosspoint faults in programmable logic arrays (PLA´s). The control input procedure developed here can be used to convert PLA´s having undetectable crosspoint faults to crosspoint-irredundant PLA´s for testing purposes. All crosspoints will be testable in crosspoint-irredundant PLA´s. The control inputs are used as extra variables during testing. They are maintained at logic 1 during normal operation. A useful heuristic for obtaining a near-minimal number of control inputs is suggested. Expressions for calculating bounds on the number of control inputs have also been obtained.
Keywords :
Control input procedure; covering row sets; crosspoint faults; crosspoint-irredundant PLA´s; programmable logic arrays; single fault assumption; undetectable crosspoint faults; Circuit faults; Circuit testing; Decoding; Design for testability; Fault detection; Logic design; Logic testing; Programmable logic arrays; Redundancy; Reliability engineering; Control input procedure; covering row sets; crosspoint faults; crosspoint-irredundant PLA´s; programmable logic arrays; single fault assumption; undetectable crosspoint faults;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1983.1676277
