• DocumentCode
    1148856
  • Title

    A 5 V-compatible flash EEPROM cell with microsecond programming time for embedded memory applications

  • Author

    Van Houdt, J. ; Wellekens, D. ; Faraone, L. ; Haspeslagh, L. ; Deferm, L. ; Groeseneken, G. ; Maes, H.E.

  • Author_Institution
    IMEC, Leuven, Belgium
  • Volume
    17
  • Issue
    3
  • fYear
    1994
  • fDate
    9/1/1994 12:00:00 AM
  • Firstpage
    380
  • Lastpage
    389
  • Abstract
    This paper presents a split-gate flash EEPROM cell that relies on enhanced hot-electron injection onto the floating gate for fast 5 V-only programming. The device is referred to as the High Injection MOS (or HIMOS) cell and is fabricated in a 0.7-μm double polysilicon CMOS technology with minor additions to the standard CMOS process flow. The cell has been optimized for a virtual ground array configuration in order to shrink the area down to the range of 10-20 μm2 per bit. An extensive study is presented of the influence of applied programming voltages and device geometry on cell performance. It is shown that, for a cell area of 16.5 μm2, microsecond programming can be achieved with a program-gate voltage of 12 V and 5 V-only operation. Furthermore, during programming the unique features of the HIMOS cell result in very low drain current (approximately 25 μA per cell for 5 V-only operation) and a correspondingly low power consumption. It is shown experimentally that the combination of high programming efficiency with low power consumption indicates that 3.3 V-only operation is already viable in 0.7-μm technology. In addition, a detailed study of the various possible disturb effects confirms the reliability of the HIMOS technology, and the feasibility of using a virtual ground array for this memory cell
  • Keywords
    CMOS integrated circuits; EPROM; PLD programming; cellular arrays; integrated memory circuits; silicon; 0.7 micron; 12 V; 25 muA; 3.3 V; 3.3 V-only operation; 5 V; 5 V-compatibility; 5 V-only programming; HIMOS cell; Si; applied programming voltages; cell performance; device geometry; double polysilicon CMOS technology; embedded memory applications; flash EEPROM cell; high injection MOS; hot-electron injection; low power consumption; microsecond programming time; reliability; split-gate cell; virtual ground array configuration; CMOS process; CMOS technology; Costs; EPROM; Energy consumption; Geometry; Nonvolatile memory; Secondary generated hot electron injection; Split gate flash memory cells; Voltage;
  • fLanguage
    English
  • Journal_Title
    Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1070-9886
  • Type

    jour

  • DOI
    10.1109/95.311747
  • Filename
    311747