DocumentCode
1148974
Title
Equivalence of the Arbiter, the Synchronizer, the Latch, and the Inertial Delay
Author
Barros, José C. ; Johnson, Brian W.
Author_Institution
Development Company
Issue
7
fYear
1983
fDate
7/1/1983 12:00:00 AM
Firstpage
603
Lastpage
614
Abstract
An axiomatic method for proving correctness properties about digital circuit implementations under the influence of asynchronous inputs is presented. This method, termed hardware correctness, is used to prove properties about a target digital circuit that is implemented in terms of constituent digital circuits. The proof consists of deducing theorems about properties of the target circuit from known properties of the constituent circuits. Three types of properties are considered, and they are expressed as axioms in first order predicate calculus. The axioms describe ideal behavior of the four most commonly studied asynchronous circuits, the inertial delay, the synchronizer, the time-bounded arbiter, and the latch. These axioms are derived from the less precise behavioral descriptions used by other investigators.
Keywords
Arbiter; axiomatic model; inertial delay; latch; sequential circuit; synchronizer; ternary algebra; Algebra; Asynchronous circuits; Bandwidth; Calculus; Delay; Digital circuits; Digital systems; Hardware; Latches; Sequential circuits; Arbiter; axiomatic model; inertial delay; latch; sequential circuit; synchronizer; ternary algebra;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1983.1676292
Filename
1676292
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