Optimal chip sizing for multi-chip modules

Author

Singh, P. ; Landis, D.L.

Author_Institution

Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA

Volume

Issue

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

369

Lastpage

375

Abstract

The functions of a complex electronic system will be partitioned across multiple chips. An optimal system using PWB technology will contain just a few chips in order to minimize the inter-chip delays. However, the area delay penalty for inter-die interconnects is much lower for MCM technology, and different partitioning options should be considered. This paper develops a criteria for optimal MCM chip sizing based upon system quality level, cost and silicon efficiency. The criteria are then applied to a 500,000 gate MCM case study

Keywords

minimisation; multichip modules; 500000 gate MCM; Si; area delay; complex electronic system; cost; inter-die interconnects; minimization; multi-chip modules; multiple chips; optimal chip sizing; partitioning; quality level; silicon efficiency; Components, packaging, and manufacturing technology; Cost function; Delay; Electronics packaging; Integrated circuit interconnections; LAN interconnection; Logic arrays; Microprocessors; Pins; Silicon;

fLanguage

English

Journal_Title

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Publisher

ieee

ISSN

1070-9894

Type

jour

DOI

10.1109/96.311786

Filename

311786

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1149214