DocumentCode
1149455
Title
Representing the Effect of Instruction Prefetch in a Microprocessor Performance Model
Author
De Prycker, Martin
Author_Institution
Bell Telephone Manufacturing Company
Issue
9
fYear
1983
Firstpage
868
Lastpage
872
Abstract
The implementation of variable addressing and block structure has a substantial influence on the global system performance. One model dederibes this influence as a product of program statistical, architectural and technological parameters, but only for sequential processors. In this correspondence we adapt this model to processors with an instrution prefetch pipeline. An upper and lower bound for the performance measure is obtained, using a best/worst case analysis. The influence of the memory speed on the performance is also determined.
Keywords
Best/worst case; clock cycles; instruction prefetch pipeline; memory speed; performance analysis; Costs; Decoding; Hardware; High level languages; Microprocessors; Microwave integrated circuits; Performance analysis; Pipelines; Prefetching; Read only memory; Best/worst case; clock cycles; instruction prefetch pipeline; memory speed; performance analysis;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1983.1676337
Filename
1676337
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