MOS analogue circuit simulation with SPICE

Author

Vladimirescu, A. ; Chariot, J.-J.

Author_Institution

Cadence Design Syst. Inc., San Jose, CA, USA

Volume

141

Issue

4

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

265

Lastpage

274

Abstract

The paper describes implementation details and imperfections of the SPICE MOSFET models which, together with MOS circuit design techniques, can contribute to inaccurate simulation results and convergence failure. The impact of model parameters on MOS level 2 and 3 drain-source conductance and gate-drain transconductance is analysed, and discontinuities are revealed. A typical CMOS differential amplifier is used to relate design techniques to possible convergence failures. Solutions for convergence are described, based on model parameter/physical effect selection, options specification initialisation techniques and algorithmic choices. Design techniques and simulation difficulties are related to SPICE models to convey the right approach for modelling and simulating analogue MOS designs

Keywords

CMOS integrated circuits; SPICE; differential amplifiers; digital simulation; insulated gate field effect transistors; linear integrated circuits; semiconductor device models; CMOS differential amplifier; MOS analogue circuit; MOSFET models; SPICE; algorithmic choices; circuit design techniques; circuit simulation; convergence failure; drain-source conductance; gate-drain transconductance; model parameter/physical effect selection; options specification initialisation techniques;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings -

Publisher

iet

ISSN

1350-2409

Type

jour

DOI

10.1049/ip-cds:19941247

Filename

311851