Design of a low-area, high-throughput LDPC decoder using shared memory banks for DVB-S2

This paper presents a high throughput LDPC decoder architecture for DVB-S2, a second generation standard for European satellite digital video broadcasting system. DVB-S2 standard specifies higher order modulation and powerful FEC system based on LDPC codes concatenated with BCH code. DVB-S2 has been gradually replacing DVB-S for global satellite digital TVs, and many HDTV channels are served by DVB-S2 standard in Europe and Japan. The proposed decoder architecture clusters bitnodes and checknodes into groups by utilizing of periodic nature of parity check matrix. Each of these node groups are assigned to a functional modules which perform calculations required at bitnodes and checknodes. These functional modules exchange data through shared memory banks to maximize parallel accesses. Implementation of the proposed architecture exhibits the throughput of 277 Mbps, 9% improvements over previous architecture, while the area is reduced by as much as 52%.