DocumentCode :
1149764
Title :
Modular Matrix Multiplication on a Linear Array
Author :
Ramakrishnan, I.V. ; Varman, Peter J.
Author_Institution :
Department of Computer Science, University of Maryland
Issue :
11
fYear :
1984
Firstpage :
952
Lastpage :
958
Abstract :
A matrix multiplication algorithm on a linear array of processing elements is described. The local storage required by the processing elements and the I/O bandwidth required to drive the array are both constants that are independent of the sizes of the matrices being multiplied. The algorithm is therefore modular, that is, arbitrarily large matrices can be multiplied on a large array built by cascading smaller arrays. Each of the matrix elements is read only once from a fixed I/O port and the algorithm does not use global broadcasting. It is also shown that the proposed algorithm computes the n3 scalar products (where n is the size of the two matrices being multiplied) using an optimal number of processing elements.
Keywords :
Array processors; VLSI; linear array; matrix multiplication; modular; parallel processing; Application software; Bandwidth; Broadcasting; Clocks; Computer peripherals; Parallel processing; Pipeline processing; Synchronization; Very large scale integration; Wire; Array processors; VLSI; linear array; matrix multiplication; modular; parallel processing;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1984.1676369
Filename :
1676369
Link To Document :
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