Title :
Parallel contention resolution control for input queueing ATM switches
Author :
Obara, Hiromichi
Author_Institution :
NTT Transmission Syst. Labs., Yokosuka, Japan
fDate :
4/23/1992 12:00:00 AM
Abstract :
Input queueing ATM switches requiring fast contentional resolution control have been negatively affected by long turn-around time (TAT) due to the distance between an input port controller and a centralised contention controller. A parallel contention resolution control for input queueing switches is presented. The proposed control allows a TAT of more than one cell slot, resulting in the potential development of a centralised contention controller for an ATM switch with an aggregate capacity of 1 Tbit/s.
Keywords :
electronic switching systems; pipeline processing; queueing theory; telecommunications control; time division multiplexing; 1 Tbit/s; centralised contention controller; input port controller; input queueing ATM switches; long turn-around time; parallel contention resolution control; pipelining technique;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19920530
