Title :
Cofactor packing algorithm for lookup-table based field programmable gate arrays
Author :
Park, S.S. ; Lee, Y.H. ; Hwang, Su Hwan ; Kyung, Chong-Min
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul
fDate :
7/21/1994 12:00:00 AM
Abstract :
The authors present a new technology mapping algorithm for an LUT-based FPGA. Decomposition of a Boolean network is formulated as an algebraic cofactoring, and the technology mapping is performed by cofactor packing. Experimental results show that the proposed method decomposes infeasible nodes in a shorter CPU time with more than 10% reduced number of nodes compared with previous decomposition methods
Keywords :
Boolean functions; logic CAD; logic arrays; table lookup; Boolean network decomposition; CPU time; algebraic cofactoring; cofactor packing algorithm; field programmable gate arrays; lookup-table based FPGA; technology mapping;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19940862
