DocumentCode
1150137
Title
Dual-modulus frequency dividers with minimum gate count
Author
Wennekers, P.
Author_Institution
Semiconductor Product Sector, Motorola Inc., Tempe, AZ
Volume
30
Issue
15
fYear
1994
fDate
7/21/1994 12:00:00 AM
Firstpage
1198
Lastpage
1199
Abstract
A method for minimising the gate count in dual-modulus frequency dividers is presented. The gate count is minimised by identification of a set of Boolean equations with one type of Boolean operator only, using internal gates of D-flipflops to realise the Boolean functions. Circuit diagrams for divide-by-2/3 and divide-by-4/5 static frequency dividers are shown. The minimised circuits have higher speed and lower power consumption compared to conventional solutions because additional gates are not required
Keywords
Boolean functions; flip-flops; frequency dividers; logic design; minimisation of switching nets; sequential circuits; Boolean equations; Boolean functions; D-flipflops; dual-modulus frequency dividers; identification; minimum gate count; static frequency dividers;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19940829
Filename
311905
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