A Computer Aided Procedure for Performing Static Loading Validation of Digital Logic Systems

A logic network is modeled with logic elements and a set of junctions formed by the interconnection of logic element pins. Electrical models for logic element pins are developed that include appropriate current and voltage parameters, and a consistent set of nomenclature for these parameters is introduced. An algorithm is then presented that can be used to determine the ability of ap element pin to force its junction to one or both of its valid logic states. The junctions may include bidirectional logic elements and wired-high and wired-low configurations. The algorithm evaluates every junction in the network and produces both error (fatal failure) and warning (possible failure) messages for each junction. This can be viewed as a "loading check" on the network. The noise margin for each junction is also computed and compared to a preselected value. Examples of the application of this algorithm on practical TTL circuits are presented.