Title :
Design and Application of Self-Testing Comparators Implemented with MOS PLA´s
Author :
Tamir, Yuval ; Sequin, Carlo H.
Author_Institution :
Computer Science Division, Department of Electrical Engineering and Computer Sciences, University of California
fDate :
6/1/1984 12:00:00 AM
Abstract :
A high probability of detecting errors caused by hardware faults is an essential property of any fault-tolerant system. VLSI technology makes the use of duplication and matching for error detection practical and attractive. A critical circuit in this context is a self-testing comparator. Faults in the comparator must be detected so that they do not mask discrepancies between the duplicated modules.
Keywords :
Concurrent error detection; MOS PLA fault model; duplication and matching; faults in VLSI circuits; programmable logic array; self-testing comparator; two-rail code checker; Built-in self-test; Circuit faults; Computer errors; Electrical fault detection; Fault detection; Fault tolerant systems; Hardware; Programmable logic arrays; Semiconductor device modeling; Very large scale integration; Concurrent error detection; MOS PLA fault model; duplication and matching; faults in VLSI circuits; programmable logic array; self-testing comparator; two-rail code checker;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1984.1676473
