DocumentCode
1150789
Title
Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs
Author
Hughes, Joseph L A ; McCluskey, Edward J. ; Lu, David J.
Author_Institution
Center for Reliable Computing, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University
Issue
6
fYear
1984
fDate
6/1/1984 12:00:00 AM
Firstpage
546
Lastpage
550
Abstract
Two new general designs for totally self-checking (TSC) comparators with an arbitrary number of input vectors are presented. The multipattern comparator combines modified TSC 2-input comparators and a TSC two-rail checker that requires only four patterns for self-testing. The counter-driven comparator adds circuitry to generate an exhaustive set of test patterns. The designs are compared on the basis of input limitations, circuit complexity, and gate delays. It is shown that TSC comparators cannot exist under two sets of conditions associated with 1-bit input vectors and two-level circuit realizations.
Keywords
Comparator; equality checker; permuter; totally self-checking; two-rail checker; Circuit faults; Circuit testing; Complexity theory; Delay; Electrical fault detection; Fault detection; Logic design; Logic devices; Monitoring; Test pattern generators; Comparator; equality checker; permuter; totally self-checking; two-rail checker;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1984.1676478
Filename
1676478
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