DocumentCode
1150842
Title
Fault Tolerance in Binary Tree Architectures
Author
Raghavendra, C.S. ; AVIvizienis ; Ercegovac, M.D.
Author_Institution
Department of Electrical Engineering-Systems, University of Southern California
Issue
6
fYear
1984
fDate
6/1/1984 12:00:00 AM
Firstpage
568
Lastpage
572
Abstract
Binary tree network architectures are applicable in the design of hierarchical computing systems and in specialized high-performance computers. In this correspondence, the reliability and fault tolerance issues in binary tree architecture with spares are considered. Two different fault-tolerance mechanisms are described and studied, namely: 1) scheme with spares; and 2) scheme with performance degradation. Reliability analysis and estimation of the fault-tolerant binary tree structures are performed using the interactive ARIES 82 program. The discussion is restricted to the topological level, and certain extensions of the schemes are also discussed.
Keywords
Binary tree; fault tolerance; network architecture; performance degradation; reliability modeling; spare processors; Binary trees; Computer architecture; Error correction; Fault tolerance; Fault tolerant systems; Notice of Violation; Operating systems; Software measurement; Software reliability; Timing; Binary tree; fault tolerance; network architecture; performance degradation; reliability modeling; spare processors;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1984.1676483
Filename
1676483
Link To Document