DocumentCode
1151403
Title
Multiple fault detection in parity checkers
Author
Jone, Wen-Ben ; Wu, Cheng-Juei
Author_Institution
Dept. of Comput. Sci., New Mexico Tech., Socorro, NM, USA
Volume
43
Issue
9
fYear
1994
fDate
9/1/1994 12:00:00 AM
Firstpage
1096
Lastpage
1099
Abstract
Parity checkers are widely used in digital systems to detect errors when systems are in operation. Since parity checkers are monitoring circuits, their reliability must be guaranteed by performing a thorough testing. In this work, multiple fault detection of parity checkers is investigated. We have found that all multiple stuck-at faults occurring on a parity tree can be completely detected using test patterns provided by the identity matrix plus zero vector. The identity matrix contains 1´s on the main diagonal and 0´s elsewhere; while the zero vector contains 0´s. The identity matrix vectors can also detect all multiple general bridging faults, if the bridgings result in a wired-AND effect. However, test patterns generated from the identity matrix and binary matrix are required to detect a majority of the multiple bridging faults which yield wired-OR connections. Note that the binary matrix contains two 1´s at each column of the matrix
Keywords
fault location; logic testing; binary matrix; digital systems; identity matrix; monitoring circuits; multiple fault detection; multiple stuck-at faults; parity checkers; reliability; wired-OR connections; zero vector; Application software; Circuit faults; Circuit testing; Computer science; Digital systems; Electrical fault detection; Fault detection; Performance evaluation; Registers; Test pattern generators;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.312118
Filename
312118
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