• DocumentCode
    1151475
  • Title

    No clock, no bus - no sweat [asynchronous IC interconnect network]

  • Author

    Dettmer, Roger

  • Volume
    50
  • Issue
    9
  • fYear
    2004
  • Firstpage
    36
  • Lastpage
    39
  • Abstract
    This article presents a UK start-up which believes it has come up with a fundamental shift in interconnection technology that will solve timing closure problems in complex chips. It is based on an asynchronous design and uses packet switching technology. It is expected to be particularly effective in SoC design.
  • Keywords
    asynchronous circuits; integrated circuit interconnections; logic design; packet switching; system-on-chip; timing; IC interconnect network; SoC design; asynchronous design; chip timing closure problems; packet switching technology;
  • fLanguage
    English
  • Journal_Title
    IEE Review
  • Publisher
    iet
  • ISSN
    0953-5683
  • Type

    jour

  • DOI
    10.1049/ir:20040901
  • Filename
    1352745
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1151475