Title :
Address Generation in an Array Processor
Author_Institution :
Department of Computer Science, University of Port Harcourt
Abstract :
This correspondence describes the implementation of a versatile hardware address indexing unit (AIU) capable of generating a multiplicity of address sequences for both array processing and array manipulation. The AIU utilizes a counter/multiplexer principle and incorporates an address logic for implementing real-value FFT based on a standard complex form.
Keywords :
Address indexing unit; array processing and manipulation; counter/multiplexer principle; real-value FFT; Array signal processing; Counting circuits; Digital signal processing; Hardware; Indexing; Logic; Multiplexing; Samarium; Signal processing algorithms; Vibration control; Address indexing unit; array processing and manipulation; counter/multiplexer principle; real-value FFT;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1985.1676554
