DocumentCode
1151654
Title
An Analysis of Processor-Memory Interconnection Networks
Author
Bhuyan, Laxmi N.
Author_Institution
Department of Electrical and Computer Engineering, University of Southwestern Louisiana
Issue
3
fYear
1985
fDate
3/1/1985 12:00:00 AM
Firstpage
279
Lastpage
283
Abstract
An interference analysis of the interconnection networks (IN´s) for tightly coupled multiprocessors is presented in this correspondence. The interconnections considered are crossbars and delta networks. Two situations are examined: when a memory module is equally likely to be addressed by a processor and when a processor has a favorite memory. It is shown that for a higher rate of favorite requests, the delta networks perform close to a crossbar.
Keywords
Bandwidth; crossbar switches; favorite memories; multiprocessor performance; multistage interconnection networks; Bandwidth; Computer architecture; Intelligent networks; Interference; Joining processes; Multiprocessing systems; Multiprocessor interconnection networks; Switches; Synchronous generators; Very large scale integration; Bandwidth; crossbar switches; favorite memories; multiprocessor performance; multistage interconnection networks;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1985.1676571
Filename
1676571
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