DocumentCode :
1151746
Title :
Vector-Reduction Techniques for Arithmetic Pipelines
Author :
Ni, Lionel M. ; Hwang, Kai
Author_Institution :
Department of Computer Science, Michigan State University
Issue :
5
fYear :
1985
fDate :
5/1/1985 12:00:00 AM
Firstpage :
404
Lastpage :
411
Abstract :
Vector-reduction arithmetic accepts vectors as inputs and produces scalars as outputs. This class of vector operation forms the basis of many scientific computations, such as inner product and finding the maximum among the vector components. Vector reduction on a pipeline processor demands a feedback connection around the pipeline. Since the output of such a pipeline depends on the previous output, improper control of the feedback input may destroy the benefit from pipelining. Two new vector-reduction techniques are proposed in this paper. In addition to saving reduction time and eliminating intermediate storage (as compared to Kuck´s method and Kogge´s method), the new methods will greatly simplify the machine-level programming effort needed to implement vector-reduction operations. An interleaved technique is introduced to reduce multiple vectors to corresponding scalars using the same arithmetic pipeline. The pipeline can be fully utilized by interleaving multiple vector-reduction processes. The proposed techniques can be applied to improve the performance of vector-arithmetic pipelines in scientific supercomputers.
Keywords :
Arithmetic pipelines; VLSI architecture; interleaving; matrix algebra; multiple vector processing; vector reduction; Computer architecture; Computer science; Convolution; Digital arithmetic; Interleaved codes; Matrices; Output feedback; Pipeline processing; Supercomputers; Very large scale integration; Arithmetic pipelines; VLSI architecture; interleaving; matrix algebra; multiple vector processing; vector reduction;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1985.1676580
Filename :
1676580
Link To Document :
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