A diagonal active-area stacked capacitor DRAM cell with storage capacitor on bit line

Author

Kimura, Shin Ichiro ; Kawamoto, Yoshifumi ; Kure, Tokuo ; Hasegawa, Norio ; Kisu, Teruaki ; Etoh, Jun ; Aoki, Masakazu ; Takeda, Eiji ; Sunami, Hideo ; Itoh, Kiyoo

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

37

Issue

3

fYear

1990

fDate

3/1/1990 12:00:00 AM

Firstpage

737

Lastpage

743

Abstract

A stacked-capacitor (STC) cell concept for 16-Mb DRAMs is introduced. The STC cell features a storage capacitor placed on a bit line and a diagonal active area. This enables a large storage capacitance, 35 fF/b, to be achieved on a 3.36-μm² cell. By eliminating completely the structural interferences between bit line and plate electrode, the storage-node pattern is maximized. The STC cell also features low noise characteristics due to its shielded bit-line structure. This minimizes the interbit-line capacitance to below 1% of the bit-line capacitance in the memory array. The average charge retention time, measured using an experimental 2-kb array, is 30 s at 40°C. The characteristics of the diagonal active memory cell transistor are comparable to those of a conventional transistor

Keywords

integrated memory circuits; random-access storage; 16 Mbit; 30 s; 40 C; STC cell; average charge retention time; bit line; diagonal active memory cell transistor; diagonal active-area stacked capacitor DRAM cell; interbit-line capacitance; memory array; plate electrode; shielded bit-line structure; storage capacitor; storage-node pattern; Capacitance; Capacitors; Charge measurement; Current measurement; Electrodes; Epitaxial growth; Fabrication; Interference elimination; Random access memory; Time measurement;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.47780

Filename

47780