DocumentCode
1152143
Title
Ensuring Fault Tolerance of Phase-Locked Clocks
Author
Krishna, C.M. ; Shin, Kang G. ; Butler, Ricky W.
Author_Institution
Department of Electrical and Computer Enginieering, University of Massachusetts
Issue
8
fYear
1985
Firstpage
752
Lastpage
756
Abstract
Processors within a real-time multiprocessor system must be synchronized with as little overhead as possible. Although synchronization can be achieved via both software (e.g., interactive convergence and interactive consistency algorithms) and hardware (e.g., multistage synchronizers and phase-locked clocks), phase-locked clocks are most attractive due to their small overheads.
Keywords
Interactive consistency and interactive convergence algorithms; malicious failure; phase-locked clocks; synchronization; Clocks; Convergence; Error correction; Fault tolerance; Frequency estimation; Hardware; Multiprocessing systems; NASA; Phase estimation; Synchronization; Interactive consistency and interactive convergence algorithms; malicious failure; phase-locked clocks; synchronization;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1985.1676622
Filename
1676622
Link To Document