Title :
Design and implementation of differential pulsewidth control loop for GHz VLSI systems
Author_Institution :
Dept. of Electron. Eng., Fu Jen Catholic Univ., Taipei, Taiwan
Abstract :
A novel differential pulsewidth control loop (PWCL) is proposed, in which a balanced charge pump is employed so that the PWCL does not require a 50% duty cycle reference clock. A test chip is realised in a 0.35 μm CMOS process, and the measured results show that the tuning range for the duty cycle of the input clock is from 27 to 71% at 1 GHz operating frequency.
Keywords :
CMOS digital integrated circuits; VLSI; cascade control; circuit feedback; circuit tuning; clocks; integrated circuit design; 0.35 micron; 1 GHz; CMOS process; GHz VLSI systems; balanced charge pump; cascaded control; differential feedback control; differential pulsewidth control loop; duty cycle reference clock; test chip; tuning range;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20051882
