Static Phase Offset in a Multiplying Phase Detector

This article analyzes the static phase offset DeltaPhiO of a Gilbert cell phase detector, and attributes the majority of the offset to intrinsic channel transit time. A 6.5 GHz phase detector fabricated in a standard 0.18 mum CMOS technology is used for the study. The static phase offset is broken down into layout and intrinsic contributions, and a simple model is used to calculate the intrinsic component. The use of analytical equations for current and intrinsic phase offset results in prediction of the intrinsic static phase offset to within 12% for the current ranges considered. The use of the intrinsic model with extracted parasitics is then shown via analysis, simulation and experimental data to be useful in predicting the phase detector static phase offset. The analysis, confirmed by measurements, indicates the degree to which the static phase offset can be reduced by increasing the tail bias current.