DocumentCode
1152554
Title
Global Flow Analysis in Automatic Logic Design
Author
Trevillyan, L. ; Joyner, W. ; Berman, L.
Author_Institution
IBM Thomas J. Watson Research Center
Issue
1
fYear
1986
Firstpage
77
Lastpage
81
Abstract
This correspondence concerns applications of optimization techniques based on global flow analysis to the automated design of logic. Previous optimization work on logic design has relied primarily on either local transformations on the circuit graph or on the use of two-level Boolean minimization. Our methods involve linear time algorithms which extend the scope of local optimizations to the entire design. Their use, in some cases, has resulted in a reduction in gate count, in improved control over path length, and in better detection and elimination of redundancy.
Keywords
Automatic logic design; PLA´s; compilers; control logic; global flow analysis; Automatic logic design; PLA´s; compilers; control logic; global flow analysis;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1986.1676664
Filename
1676664
Link To Document