A drive-level error rate model for component design and system evaluation

Author

Sobey, Charles H. ; Lansky, Richard M. ; Perkins, Tim

Author_Institution

Appl. Magnetics Corp., Goleta, CA, USA

Volume

30

Issue

2

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

269

Lastpage

274

Abstract

A drive-level model for gated peak detection channels in the presence of off-track interference is presented. Input to the model can be digitized readback patterns from testers, disk drives, or recording process simulations. The model predicts bit error rate as a function of amplitude qualification threshold in the form of a threshold error rate (TER) plot. Data patterns are described which increase the likelihood of the three types of errors in gated peak detection disk drives: drop-ins, drop-outs and shifted bits. The importance of designing for drive-level performance, rather than component-level performance is discussed. Examples of using the model to determine design targets for head, media and channel parameters are given for inductive and magnetoresistive applications. The optimum design targets for some key parameters are found to change in the presence of off-track interference

Keywords

detector circuits; error analysis; magnetic heads; magnetic recording; amplitude qualification threshold; bit error rate; channel parameters; component-level performance; digitized readback patterns; drive-level error rate model; drop-ins; drop-outs; gated peak detection channels; head parameters; inductive head; magnetoresistive head; off-track interference; recording media parameters; recording process simulation; threshold error rate plot; Bit error rate; Disk drives; Disk recording; Error analysis; Interference; Magnetic heads; Magnetoresistance; Predictive models; Qualifications; Testing;

fLanguage

English

Journal_Title

Magnetics, IEEE Transactions on

Publisher

ieee

ISSN

0018-9464

Type

jour

DOI

10.1109/20.312271

Filename

312271