Title :
Exact path delay fault coverage with fundamental ZBDD operations
Author :
Padmanaban, Saravanan ; Michael, Maria K. ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
fDate :
3/1/2003 12:00:00 AM
Abstract :
We formulate the path delay fault (PDF) coverage problem as a combinatorial problem that amounts to storing and manipulating sets using a special type of binary decision diagrams, called zero-suppressed binary decision diagrams (ZBDD). The ZBDD is a canonical data structure inherently having the property of representing combinational sets very compactly. A simple modification of the proposed basic scheme allows us to increase significantly the storage capability of the data structure with minimal loss in the fault coverage accuracy. Experimental results on the ISCAS85 benchmarks show considerable improvement over all existing techniques for exact PDF grading. The proposed methodology is simple, it consists of a polynomial number of increasingly efficient ZBDD-based operations, and can handle very large test sets that grade very large number of faults.
Keywords :
automatic testing; binary decision diagrams; combinational circuits; combinatorial mathematics; data structures; delays; fault simulation; integrated circuit testing; integrated logic circuits; logic testing; ISCAS85 combinational circuits; binary decision diagrams; canonical data structure; combinational sets; combinatorial problem; delay fault testing; exact path delay fault coverage; fault coverage accuracy; fault grading; fault simulation; fundamental ZBDD operations; path delay fault coverage problem; storage capability; zero-suppressed BDD; Associate members; Benchmark testing; Boolean functions; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Data structures; Delay; Polynomials;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2002.807891