Testing ASICs with multiple identical cores

Author

Wu, Yuejian ; MacDonald, Paul

Author_Institution

Nortel Networks, Ottawa, Ont., Canada

Volume

22

Issue

3

fYear

2003

fDate

3/1/2003 12:00:00 AM

Firstpage

327

Lastpage

336

Abstract

Predesigned cores and reusable modules are popularly used in the design of large and complex application specific integrated circuits (ASICs). As the size and complexity of ASICs increase, the test effort, including test development effort, test data volume, and test application time, has also significantly increased. This paper shows that this test effort increase can be minimized for ASICs that consist of multiple identical cores. A novel design for testability (DFT) technique is proposed to test ASICs with identical embedded cores. The proposed technique significantly reduces test application time, test data volume, and test generation effort.

Keywords

application specific integrated circuits; automatic test pattern generation; built-in self test; design for testability; integrated circuit design; integrated circuit testing; logic testing; ASIC testing; ATPG; BIST; DFT technique; application specific ICs; design for testability technique; embedded cores; multiple identical cores; test application time reduction; test data volume reduction; test generation effort reduction; Application software; Application specific integrated circuits; Automatic testing; Built-in self-test; Circuit testing; Costs; Design for testability; Life testing; Logic testing; Production;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2002.807889

Filename

1182077