Erase and Retention Improvements in Charge Trap Flash Through Engineered Charge Storage Layer

Author

Goel, N. ; Gilmer, D.C. ; Park, H. ; Diaz, V. ; Sun, Y. ; Price, J. ; Park, C. ; Pianetta, P. ; Kirsch, P.D. ; Jammy, R.

Author_Institution

FEP Group at SEMATECH, Austin, TX

Volume

30

Issue

3

fYear

2009

fDate

3/1/2009 12:00:00 AM

Firstpage

216

Lastpage

218

Abstract

The simultaneous improvement in the erase and retention characteristics in a TANOS (TaN-Al₂O₃-Si₃N₄-SiO₂-Si) flash memory transistor by utilizing the band-engineered and compositionally graded SiN_x trap layer is demonstrated. With the process optimizations, a > 4V memory window and excellent 150 degC 24-h retention (0.1-0.5 V charge loss) for a programmed DeltaV_t = 4V with respect to the initial state are obtained. The band-engineered SiN_x charge storage layer enables flash scaling beyond the floating-gate technology with a promise for improved erase speed, retention, lower supply voltages, and multilevel cell applications.

Keywords

aluminium compounds; flash memories; silicon compounds; tantalum compounds; TaN-Al₂O₃-Si₃N₄-SiO₂-Si; charge storage layer; charge trap flash memories; erase improvement; floating-gate technology; memory window; retention improvement; temperature 150 degC; time 24 h; Memory; NAND; TANOS; retention;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2009.2012397

Filename

4781551