Erase and Retention Improvements in Charge Trap Flash Through Engineered Charge Storage Layer

The simultaneous improvement in the erase and retention characteristics in a TANOS (TaN-Al₂O₃-Si₃N₄-SiO₂-Si) flash memory transistor by utilizing the band-engineered and compositionally graded SiN_x trap layer is demonstrated. With the process optimizations, a > 4V memory window and excellent 150 degC 24-h retention (0.1-0.5 V charge loss) for a programmed DeltaV_t = 4V with respect to the initial state are obtained. The band-engineered SiN_x charge storage layer enables flash scaling beyond the floating-gate technology with a promise for improved erase speed, retention, lower supply voltages, and multilevel cell applications.