DocumentCode :
1153564
Title :
Five-Step (Pad–Pad Short–Pad Open–Short–Open) De-Embedding Method and Its Verification
Author :
Kang, In Man ; Jung, Seung-Jae ; Choi, Tae-Hoon ; Jung, Jae-Hong ; Chung, Chulho ; Kim, Han-Su ; Oh, Hansu ; Lee, Hyun Woo ; Jo, Gwangdoo ; Kim, Young-Kwang ; Kim, Han-Gu ; Kyu-Myung Choi
Author_Institution :
Syst. LSI Div., Samsung Electron., Yongin
Volume :
30
Issue :
4
fYear :
2009
fDate :
4/1/2009 12:00:00 AM
Firstpage :
398
Lastpage :
400
Abstract :
We present the method for five-step (pad-pad short-pad open-short-open) on-chip parasitic de-embedding. Its validation is verified by gate electrode resistance and input capacitance of transistors based on 45 -nm CMOS process. Optimized dummy structures to remove the parasitic components due to the pad and routing metal are proposed. Parameters extracted by the proposed method have excellent physical and theoretical trends.
Keywords :
MOSFET; S-parameters; RF MOSFET; five-step de-embedding method; gate electrode resistance; input capacitance; on-chip parasitic de-embedding; on-wafer RF measurement; Gate electrode resistance; RF MOSFETs; input capacitance; on-wafer RF measurement; parasitic de-embedding;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2009.2013881
Filename :
4781577
Link To Document :
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