Title :
Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams
Author :
Abadir, Magdy S. ; Reghbati, Hassan K.
Author_Institution :
Department of Electrical Engineering–Systems, University of Southern California
fDate :
4/1/1986 12:00:00 AM
Abstract :
This correspondence presents a test generation methodology for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers, adders, RAM´s, and MUX´s. The functions of the individual modules are described using binary decision diagrams. A functional fault model is developed independent of the implementation details of the circuit. A generalized D algorithm is proposed for generating tests to detect functional as well as gate-level faults. Algorithms which perform fault excitation, implication, D propagation, and line justification on the functional modules are also described.
Keywords :
Binary decision diagrams; D algorithm; fault detection; fault model; functional faults; functional test generation; Adders; Boolean functions; Circuit faults; Circuit testing; Data structures; Digital circuits; Electrical fault detection; Fault detection; Registers; Very large scale integration; Binary decision diagrams; D algorithm; fault detection; fault model; functional faults; functional test generation;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1986.1676774