DocumentCode
1153761
Title
A Study of Pipelining in Computing Arrays
Author
Jagadish, Hosagrahar V. ; Mathews, Rob G. ; Kailath, Thomas ; Newkirk, John A.
Issue
5
fYear
1986
fDate
5/1/1986 12:00:00 AM
Firstpage
431
Lastpage
440
Abstract
In this paper, we take a hard look at scheduling considerations in computing arrays. A simple sufficient condition is developed for determining whether a computing array can be pipelined. If the array cannot be pipelined in the form given, the condition also indicates the direction in which to proceed to make it pipelineable. The overall framework and methodology take a good part of the load off the logical architect of the array, and make the translation from the logical to the physical architecture a mechanical process.
Keywords
Pipelining; systolic array; Circuits; Information systems; Laboratories; Logic arrays; Pipeline processing; Processor scheduling; Sufficient conditions; Systolic arrays; Throughput; Very large scale integration; Pipelining; systolic array;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1986.1676785
Filename
1676785
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