DocumentCode
1154110
Title
Yield learning and the sources of profitability in semiconductor manufacturing and process development
Author
Weber, C.
Author_Institution
Dept. of Eng. & Technol. Manage., Portland State Univ., OR, USA
Volume
17
Issue
4
fYear
2004
Firstpage
590
Lastpage
596
Abstract
A numerical model that identifies the high-leverage variables associated with profitability in semiconductor manufacturing is presented. Varying the parameters of the model demonstrates that a rapid yield-learning rate determines profitability more than any other factor does. Factors such as ramping-up early, adding fab capacity, depressing the terminal fault density, and shrinking die size all yield diminishing returns. The model also suggests that developing a rapid problem-solving capability in the early stages of process development enables successful yield learning.
Keywords
MIS structures; electronics industry; integrated circuit economics; integrated circuit yield; MIS structures; fab capacity; high-leverage variables; rapid problem-solving capability; rapid yield-learning rate; semiconductor manufacturing; semiconductor process development; shrinking die size; terminal fault density; Electronics industry; Fabrication; Integrated circuit modeling; Manufacturing processes; Numerical models; Profitability; Semiconductor device manufacture; Semiconductor device modeling; Semiconductor process modeling; Virtual manufacturing; Profitability; semiconductor manufacturing; yield learning;
fLanguage
English
Journal_Title
Semiconductor Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
0894-6507
Type
jour
DOI
10.1109/TSM.2004.835724
Filename
1353315
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