DocumentCode
1154167
Title
Delay-fault diagnosis using timing information
Author
Wang, Zhiyuan ; Marek-Sadowska, Malgorzata M. ; Tsai, Kun-Han ; Rajski, Janusz
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, CA, USA
Volume
24
Issue
9
fYear
2005
Firstpage
1315
Lastpage
1325
Abstract
In modern technologies, process variations can be quite substantial, often causing design timing failures. It is essential that those errors be correctly and quickly diagnosed. Unfortunately, the resolution of the existing delay-fault diagnostic methodologies is still unsatisfactory. In this paper, the feasibility of using the circuit timing information to guide the delay-fault diagnosis is investigated. A novel and efficient diagnostic approach based on the delay window propagation (DWP) is proposed to achieve significantly better diagnostic results than those of an existing delay-fault diagnostic commercial tool. Besides locating the source of the timing errors, for each identified candidate the proposed method determines the most probable delay defect size. The experimental results indicate that the new method diagnoses timing faults with very good resolution.
Keywords
circuit analysis computing; delays; failure analysis; fault simulation; logic testing; timing jitter; DWP; circuit timing information; delay defect size; delay testing; delay window propagation; delay-fault diagnosis; error correction; fault diagnosis; logic simulation; timing analysis; timing errors; timing failures; timing faults; Analytical models; Circuit faults; Circuit simulation; Computational modeling; Computer graphics; Failure analysis; Logic testing; Propagation delay; Time to market; Timing; Delay testing; fault diagnosis; logic simulation; simulation; timing analysis;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2005.852062
Filename
1501897
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