Title :
In-line defect reduction from a historical perspective and its implications for future integrated circuit manufacturing
Author :
Guldi, Richard L.
Author_Institution :
Texas Instruments, Dallas, TX, USA
Abstract :
The enormous progress in integrated circuit manufacturing over the last 30 years would have been impossible without the science of yield enhancement and defect reduction. This paper traces the evolution of this science, reviewing the history of defect inspection tooling, the practices developed for finding root causes of defects, yield modeling techniques, and important defectivity issues for current generation copper and low-K dielectric metallization. Based on the historical perspective and current status of yield enhancement technology, the paper anticipates future developments required to extend yield learning to sub-0.1-μm technology generations.
Keywords :
copper; inspection; integrated circuit manufacture; integrated circuit metallisation; integrated circuit yield; substrates; surface contamination; 0.1 micron; Cu; copper; defect inspection; defect reduction; integrated circuit manufacturing; low-K dielectric metallization; yield enhancement; yield modeling; History; Inspection; Integrated circuit manufacture; Integrated circuit technology; Integrated circuit yield; Manufacturing processes; Metallization; Paper technology; Sampling methods; Substrates; 65; Defect root cause analysis; historical yield learning; in-line defect inspection; yield modeling;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
DOI :
10.1109/TSM.2004.835717