DocumentCode :
1154206
Title :
Calligrapher: a new layout-migration engine for hard intellectual property libraries
Author :
Zhu, Jianwen ; Fang, Fang ; Tang, Qianying
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Ont., Canada
Volume :
24
Issue :
9
fYear :
2005
Firstpage :
1347
Lastpage :
1361
Abstract :
Modern systems-on-a-chip depend heavily on hard intellectual properties, such as standard cell and datapath libraries. As the foundries accelerate their update of advanced processes with increasingly complex design rules, and the libraries grow in flexibility and size, the cost of library development becomes prohibitively high. Automated layout-migration techniques used today, which are based on layout compaction developed a decade ago, corrupt advanced design considerations by honoring only design rules, and cannot cope with some of the new challenges involved. In this paper, we present a new integer linear programming (ILP)-based layout-migration engine, called calligrapher, and make the following contributions. First, we extend the recently proposed minimum perturbation (MP) metric designed to retain original layout design intentions, while overcoming its shortcoming of biased treatment of layout objects. Second, we propose a new design-rule-constraint algorithm, and prove its linear complexity for the number of constraints generated. Compared with what has been achieved in the literature, the proposed algorithm can significantly reduce the ILP solver time by limiting the constraint size. Third, we propose an iterative migration framework based on the concept of soft constraint. With this framework, two-dimensional compaction quality can be achieved with a runtime comparable to one-dimensional compaction. We demonstrate the effectiveness of calligrapher by migrating the Berkeley low-power libraries, originally developed for the 1.2-μm MOSIS process, into TSMC 0.25- and 0.18-μm technologies. We show that even for a very compact layout, our metric and the MP metric can make a difference by as much as 20%-45%. We also show that our iterative algorithm can improve the area by 10% on average compared to the traditional technique using the MP metric, and inflates the area by merely 7.5% compared to the traditional technique using minimum-area metric.
Keywords :
circuit analysis computing; circuit layout CAD; integrated circuit layout; linear programming; system-on-chip; Berkeley low-power libraries; ILP; MOSIS process; TSMC; automated layout migration techniques; calligrapher; datapath library; design reuse; design-rule-constraint algorithm; hard intellectual property libraries; integer linear programming; iterative migration framework; layout compaction; layout design; layout-migration engine; minimum perturbation metric design; soft constraint; standard cell library; systems-on-a-chip depend; Acceleration; Algorithm design and analysis; Compaction; Costs; Engines; Foundries; Integer linear programming; Intellectual property; Iterative algorithms; Libraries; Design reuse; layout compaction; layout migration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2005.852040
Filename :
1501900
Link To Document :
بازگشت