Novel 4:1 multiplexer circuit for Gbit/s data rates

A new high-speed multiplexer integrated circuit topology capable of handling four simultaneous data channels without external delay lines is described. The circuit proposed features an inherently fast two-stage configuration with a simulated data rate of 10 Gbit/s based on a submicron silicon bipolar technology. The system clock frequency is one half of the bit rate with only one additional self-generated internal clock necessary. A unique circuit topology has been chosen for acquiring and delaying the incoming data. Retiming is performed for data streams which are phase misaligned within 200 degrees .