An integrated pre-access architecture for CMOS SRAM

A proposed architecture for CMOS SRAM, random pre-access memory (RPM), allows any single word address to provide simultaneous access to multiple consecutive words starting at the given address. RPM has this pre-access feature integrated into its circuit design in order to minimize access time and increase organizational flexibility. A technique for implementing RPMs of practical size is described, and the characteristics of the memory are examined. Integrating its pre-access function in a CMOS SRAM results in no significant access time penalty, and an area cost of 2% to 8%, depending on the memory organization and size. This architecture is well suited to integrated memory whose requirements necessitate unaligned, multiword access with minimal delay penalty and no power-of-two access restrictions. In particular, such memory finds application in the instruction caches of high-performance superscalar processors, since these require multiple instruction prefetches in a single cycle