• DocumentCode
    1154411
  • Title

    Two-stage approach for 12-V VR

  • Author

    Ren, Yuancheng ; Xu, Ming ; Yao, Kaiwei ; Meng, Yu ; Lee, Fred C.

  • Author_Institution
    Center for Power Electron. Syst., State Univ., Blacksburg, VA, USA
  • Volume
    19
  • Issue
    6
  • fYear
    2004
  • Firstpage
    1498
  • Lastpage
    1506
  • Abstract
    To meet the stringent specifications of the voltage regulator (VR), the two-stage approach is proposed for the 12-V VR. This paper discusses detailed design considerations, which include the design of the first stage, optimization of the intermediate bus voltage, design of the intermediate bus capacitors, and the design of the ultra-high frequency second stage. The analysis shows that the two-stage approach can realize high frequency, thus significantly reducing the output capacitance and therefore decreasing the cost. A 1.2-V/100-A prototype is built to verify the analysis. The second stage runs at 2MHz per phase and the total efficiency is as high as 81%. Compared to the conventional single-stage multiphase buck, the two-stage approach is more cost-effective and more efficient.
  • Keywords
    busbars; capacitors; optimisation; voltage regulators; 1.2 V; 100 A; 12 V; 2 MHz; VR; intermediate bus capacitor; intermediate bus voltage; optimization; two-stage approach; ultra-high frequency second stage; voltage regulator; Buck converters; Capacitors; Costs; Design optimization; Microprocessors; Regulators; Silver; Switching frequency; Virtual reality; Voltage; 65; High frequency; VR; two-stage; voltage regulator;
  • fLanguage
    English
  • Journal_Title
    Power Electronics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0885-8993
  • Type

    jour

  • DOI
    10.1109/TPEL.2004.836678
  • Filename
    1353340