DocumentCode :
1154438
Title :
Parallel-processing techniques for automatic test pattern generation
Author :
Klenke, Robert H. ; Williams, Ronald D. ; Aylor, James H.
Author_Institution :
Dept of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
Volume :
25
Issue :
1
fYear :
1992
Firstpage :
71
Lastpage :
84
Abstract :
Some of the more widely used serial automatic test pattern generation (ATPG) algorithms and their stability for implementation on a parallel machine are discussed. The basic classes of parallel machines are examined to determine what characteristics they require of an algorithm if they are to implement it efficiently. Several techniques that have been used to parallelize ATPG are presented. They fall into five major categories: fault partitioning, heuristic parallelization, search-space partitioning, functional (algorithmic) partitioning, and topological partitioning. In each category, an overview is given of the technique, its advantages and disadvantages, the type of parallel machine it has been implemented on, and the results.<>
Keywords :
automatic testing; fault tolerant computing; logic testing; parallel processing; automatic test pattern generation; fault partitioning; functional partitioning; heuristic parallelization; parallel machine; search-space partitioning; stability; topological partitioning; Automatic test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Digital circuits; Fault detection; Logic circuits; Logic testing; Target tracking; Test pattern generators;
fLanguage :
English
Journal_Title :
Computer
Publisher :
ieee
ISSN :
0018-9162
Type :
jour
DOI :
10.1109/2.108056
Filename :
108056
Link To Document :
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