Title :
A Fast 1-D Serial-Parallel Systolic Multiplier
Author_Institution :
Department of Computer Science, Carnegie-Mellon University
Abstract :
Based on the modified Booth´s algorithm, a fast 1-D serial- parallel systolic multiplier is designed for multiplying two´s complement numbers. The circuit with countercurrent data flow pattern accepts the multiplicand serially, the multiplier in parallel, and outputs the product serially. It requires a complementer and N/2 cells, each of which contains a ripple-carry adder and some gates, where N is restricted to even. The number of clocks required to multiply an n-bit (n ≤ N) multiplier and an m-bit multiplicand is equal to n + m − 1, and independent of the circuit size N.
Keywords :
Countercurrent data flow pattern; VLSI; five-level multiplexer; five-level recorder; modified Booth´s Algorithm; systolic multilier; two´s complement; Adders; Algorithm design and analysis; Clocks; Computer science; Hardware; Integrated circuit interconnections; Integrated circuit synthesis; Very large scale integration; Wires; Wiring; Countercurrent data flow pattern; VLSI; five-level multiplexer; five-level recorder; modified Booth´s Algorithm; systolic multilier; two´s complement;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1987.1676865
