• DocumentCode
    1154889
  • Title

    Vector Computer Memory Bank Contention

  • Author

    Bailey, David H.

  • Author_Institution
    Numerical Aerodynamic Simulation Systems Division, NASA Ames Research Center
  • Issue
    3
  • fYear
    1987
  • fDate
    3/1/1987 12:00:00 AM
  • Firstpage
    293
  • Lastpage
    298
  • Abstract
    A number of recent vector supercomputer designs have featured main memories with very large capacities, and presumably even larger memories are planned for future generations. While the memory chips used in these computers can store much larger amounts of data than before, their operation speeds are rather slow when compared to the significantly faster CPU (central processing unit) circuitry in new supercomputer designs. A consequence of this speed disparity between CPU´s and main memory is that memory access times and memory bank reservation times (as measured in CPU ticks) are sharply increased from previous generations.
  • Keywords
    Interleaved memories; Markov chains; memory bank contention; supercomputers; vector computers; Central Processing Unit; Circuits; Clocks; Computational fluid dynamics; Mathematical model; NASA; Physics; Plasmas; Supercomputers; Velocity measurement; Interleaved memories; Markov chains; memory bank contention; supercomputers; vector computers;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1987.1676901
  • Filename
    1676901