Title :
Pseudorandom Testing
Author :
Wagner, Kenneth D. ; Chin, Cary K. ; McCluskey, Edward J.
Author_Institution :
EDS VLSI Design Rules Control Department, IBM
fDate :
3/1/1987 12:00:00 AM
Abstract :
Algorithmic test generation for high fault coverage is an expensive and time-consuming process. As an alternative, circuits can be tested by applying pseudorandom patterns generated by a linear feedback shift register (LFSR). Although no fault simulation is needed, analysis of pseudorandom testing requires the circuit detectability profile.
Keywords :
Detectability profile; fault coverage; pseudorandom testing; random testing; test confidence; test generation; test length; Analytical models; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Feedback circuits; Linear feedback shift registers; System testing; Test pattern generators; Detectability profile; fault coverage; pseudorandom testing; random testing; test confidence; test generation; test length;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1987.1676905
