Title :
A New Built-In Self-Test Design for PLA´s with Hligh Fault Coverage and Low Overhead
Author :
Treuer, Robert ; Agarwal, Vinod K. ; Fujiwara, Hideo
Author_Institution :
Department of Electrical Engineering, McGill University
fDate :
3/1/1987 12:00:00 AM
Abstract :
This correspondence presents a new built-in self-test design for PLA´s, that has a lower area overhead and higher multiple fault coverage (of three types of faults: crosspoint, stuck, and bridging) than any existing design. This new design uses function independent test input patterns (which are generated on chip), compresses the output responses into a function independent string of parity bits (whose fault-free expected values are generated on-line with a simple circuit), and detects all siqgle faults and more than ( 1 −−2(m+2n) of all multiple faults where m and n represent the number of product terms and input variables, respectively.
Keywords :
Built-in self test (BIST); VLSI design; fault coverage; fault models; output response compression; parity bits; programmable logic array (PLA); test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Logic arrays; Logic design; Logic testing; Programmable logic arrays; Test pattern generators; Very large scale integration; Built-in self test (BIST); VLSI design; fault coverage; fault models; output response compression; parity bits; programmable logic array (PLA); test pattern generation;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1987.1676911
